1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to the design and manufacture of floating gate memory devices such as flash electrically erasable programmable read-only memory (EEPROM) devices having improved and more uniform performance characteristics.
2. Description of the Related Art
In general, memory devices such as a flash electrically erasable programmable read only memory (EEPROM) are known. For example, referring to FIGS. 1, 2, and 2A, a flash EEPROM 100, commonly comprises a single substrate 102 in which one or more high density regions 103 and a low density peripheral portion 106 are formed. High density region 103 typically comprises at least one M.times.N array core 104 of individually addressable, identical memory cells 200 (FIGS. 2, 2A). Low density peripheral portion 106 typically includes: suitable input/output (I/O) circuitry 108, suitable circuitry for selectively addressing the individual cells, e.g., one or more x-decoder 110 and y-decoder 112; suitable circuitry 114 for selectively connecting the source, gate, and drain of selected addressed cells to predetermined voltages or impedances to effect designated operations on the cell, e.g., programming, reading and erasing, and deriving necessary voltages to effect such operations; and sensing circuitry 116 for determining whether or not an addressed cell has been programmed, i.e. is 0 or 1.
Referring now to FIGS. 2 and 2A, each cell 200 in array 104 typically comprises: source 202, drain 204, and channel 206 semiconductor regions formed in substrate 102 (or in an isolation well); and a stacked gate (word line) structure 210. Gate structure 210 suitably comprises: a thin gate dielectric layer 212 (commonly referred to as the "tunnel oxide") formed on the surface of substrate 102 overlying channel 206; a floating gate 214 overlying tunnel oxide 212; an interpoly dielectric 216 overlying floating gate 214; and a control gate 218 overlying interpoly dielectric layer 216. Cells 200 are arranged in a series of rows and columns.
In the completed array, the control gates 218 of the respective cells 200 in a row are formed integral to a common word line (WL) associated with the row. Columns of cells are arranged such that adjacent cells in a column share a common semiconductor region as source or drain regions: The source 202 of each cell in a column (excepting end cells) is formed in a common region with one of the adjacent cells, e.g., the preceding cell in the column; Likewise, the drain of the cell is formed in a common region with the drain 204 of the other adjacent cell, e.g., next succeeding cell in the column. The drain of each cell in a column of cells is connected by a conductive bit line (BL) (FIG. 2) comprising an overlying layer of metal connected to each drain 204 of the cells 200 within the column. Additionally, the sources of each cell 200 in a row (and hence pairs of rows) are interconnected by a common source line CS (FIGS. 2A) formed in substrate 102, as will be described. Any particular cell 200 within array 104 can be individually addressed (programmed and read) by operating upon one word line and one bit line.
Current is selectively conducted between source 202 and drain 204 in accordance with the electric field developed in channel 206 by gates 214, 218. By appropriately charging (programming) and discharging (erasing) floating gate 214, the threshold voltage V.sub.T of cell 200 (i.e., the voltage V.sub.G that must be applied to control gate 218 to cause current flow between source and drain above a predetermined level) may be selectively varied to program cell 200.
An individual cell 200 is programmed by charging floating gate 214 through high energy electron injection, often referred to as hot electron injection. By applying the appropriate potentials to source 202, drain 204, and control gate 218, hot electrons are injected from channel 206 through tunnel dielectric 212 to negatively charge floating gate 214. Charging floating gate 214 with a negative potential raises the threshold voltage of the cell by a predetermined amount V.sub..delta. from a first nominal value V.sub.T1 to a second nominal value V.sub.T2. As a result, a programmed cell 200 (V.sub.T &gt;V.sub.T2) conducts substantially less current during a subsequent read operation than an unprogrammed cell 200 (V.sub.T &lt;V.sub.T1) having no charge on floating gate 214.
During a read operation, common source line cs is grounded, a predetermined voltage V.sub.D is applied to the drain (via the bit line), and a predetermined voltage V.sub.G is applied to control gate 218 (the word line of the row) of the selected cell 200. If the selected cell 200 is unprogrammed (V.sub.T &lt;V.sub.T1), the gate voltage V.sub.G exceeds the threshold voltage V.sub.T1 of the cell, and cell 200 conducts a relatively high current (above a predetermined upper threshold level, e.g. 100 microamps). On the other hand, if the selected cell 200 has been programmed (V.sub.T &gt;V.sub.T2), gate voltage V.sub.G is less than the threshold voltage V.sub.T2 of the cell, and the cell is non-conductive, or at least conducts less current (below a predetermined lower threshold level, e.g. 20 microamps). The state of the cell is typically tested in sensing circuitry 116 by comparing the current output against a reference current equal to a predetermined percentage (referred to as the sense ratio) of the current from an unprogrammed cell: Conduction by the cell at a level greater than the reference current, is indicative of a first state, e.g., a zero or logical low; Conduction at a level less than the reference current is indicative of a second state, e.g., one or logical high.
The reference current is conventionally generated by an additional reference column of cells 114 formed as part of core array 104. The "bit line" of the reference column is connected to sensing circuitry 116, and the sources of the cells are grounded, rather than connected to common source line CS. The control gates of the reference cells are, however, connected to the core array wordlines. Thus, since the cells of reference column 114 remain unprogrammed (uncharged), the reference cell in the selected row conducts in response to the predetermined voltage V.sub.G applied to the wordline (and hence to the gate of the reference cell) during a read operation.
Sensing circuitry 116 typically comprises a "reference" resistive network 118 and a "sense ratio" resistive network 120, and a comparator (e.g. sense amplifier) 122. Reference resistive network 118 manifests a predetermined nominal resistance R, whereas sense ratio resistive network 120 manifests a predetermined nominal resistance equal to a predetermined multiple of the reference resistance (nR). While resistive networks are, for clarity, shown in FIG. 2 as simple resistors, in practice they typically comprise variable resistance networks that present predetermined nominal resistances in accordance with control signals applied thereto
Sense ratio resistive network 120 is effectively connected (e.g. though Y decoder 112) between the selected bit line (the drains of the cells in the selected column in array 104) and a predetermined voltage V.sub.D. Reference resistive network 118 is effectively connected between a line connecting the drains of the cells in reference column 114 and a predetermined voltage source, e.g. the same voltage V.sub.D, applied to the selected bit line (the drains of the cells in the selected column in array 104). Juncture 124 between reference resistive network 118 and the line connecting the drains of the cells in reference column 114, is connected to one input (e.g. the non-inverting input) of comparator 122. Juncture 126 between sense ratio resistive network 120 and (e.g. though Y decoder 112) the selected bit line to the other (e.g. inverting) input of comparator 122.
In a read mode, a connection is established from predetermined voltage V.sub.D (e.g., 1 to 1.5 volts) through sense ratio resistive network 120 (and Y decoder 112) to the selected bit line (and hence a voltage is provided at the drains of the cells in the selected column). The sources of the array cells are grounded. If any of the cells in the selected column are conductive, current will flow through sense ratio resistive network 120.
The cells in reference column 114 are all unprogrammed (i.e. hold no charge on the floating gates) and, indeed, are never programmed or erased in the normal course of operation. Accordingly, application of the predetermined voltage V.sub.G on the wordline will render the selected reference cell conductive, and current will flow through reference resistive network 118.
Comparator 122 generates indicia or the relative magnitudes of the current in the selected bitline and reference line. All other things being equal, the relative magnitudes of the currents is defined by the "sense ratio", i.e. the multiple (n) of resistance between resistive networks 120 and 118. Comparator 122 will indicate a programmed cell only if the bit line current is less than the reference current divided by n (i.e. I.sub.BL &lt;(1/n)I.sub.REF). Such a memory device is described in commonly assigned U.S. Pat. No. 5,335,198, issued to Van Buskirk et al. on Aug. 2, 1994.
Use of part of core array 104 to provide the reference current is advantageous in that the cells of reference column 114, formed with the operative array as part of the same process, tend to be substantially identical to the cells of the operative array 104. However, use of complete columns of cells, which may include for example, 512 cells, occupies valuable space on the semiconductor substrate.
In contrast to the programming procedure, flash EEPROMs are typically bulk-erased, so that all of cells 200 in array 104 (i.e. connected to a common source line CS) are simultaneously erased. Appropriate potentials applied to the source 202, drain 204, and control gate 218, cause electron tunneling from floating gate 214 to source 202 (or drain 204) via Fowler-Nordheim (F-N) tunneling. For example, electrons stored during programming on floating gate 214 tunnel through dielectric 212 in the area (referred to as a tunnel region 203) where floating gate 214 overlaps source region 202. F-N tunneling occurs simultaneously for all cells 200 within memory array 104, erasing entire array 104 in one "flash" or operation.
Because each cell 200 is connected to common source line CS, all cells 200 in array 104 are erased for the same amount of time. Ideally, each cell 200 in array 104 requires the same amount of time to erase,i.e. to remove electrons from floating gate 214 and achieve a lower selected threshold voltage. Erase times among cells 200 within array 104, however, differ widely. Because of the variation in erase times, each cell 200 must be erased for the amount of time required to erase the slowest cell in array 104. Erasing faster cells 200 for too long, however, results in over-erasure. Over-erasure generates a positive charge on floating gate 214, which excessively lowers the threshold voltage V.sub.T of cell 200, in some instances to the extent of establishing a negative threshold voltage (V.sub.T &lt;0). As a result, the over-erased cell 200 may be continuously activated, even when control gate 218 is grounded (V.sub.G =0 volts), so that cell 200 always conducts during a read operation, regardless of whether over-erased cell 200 is the cell selected for reading. In addition, the increase V.sub..delta. in threshold voltage effected by programming, may not be sufficient to raise the threshold voltage V.sub.T of the over-erased cell above the predetermined voltage V.sub.G applied to control gate 218 of selected cell 200, so that even when programmed, the over-erased cell conducts upon application of V.sub.G during the read process, giving an erroneous reading.
The current conducted by over-erased cells 200 in a column during a read operation is known as "column leakage current." Column leakage current manifests itself by degrading or destroying the memory's reliability and endurance. As discussed above, the bit value of a selected cell 200 depends on the magnitude of the drain current provided at the associated bit line BL. Drain 204 of each cell 200 in a column, however, is connected to the associated bit line BL. Ideally, the only cell in the column biased for possible conduction is the cell in the selected word line WL; the predetermined voltage V.sub.G is applied to the gates of cells on the selected word line and all other gates are grounded during the reading process. If selected cell 200 is unprogrammed, current in excess of the reference current (generated by application of the predetermined voltage V.sub.G to the reference cells) will be provided on the bit line, indicating e.g., a zero. If the selected cell is programmed with a "1", the drain current of the cell (and, ideally, the bit line), is below the reference current during the read operation. However, the current in the bit line reflects the cumulative current flow from all of the cells in a column. Accordingly, if any of the cells in the column are over-erased and conduct significant current during the read operation, the current flow in the bit line may be in excess of the reference current. Consequently, the read operation generates a logical zero regardless of which cell in the column is selected or whether the selected cell is programmed. In severe cases, a single over-erased cell disables the entire column. In another case, many of the cells may be slightly over-erased which provides a cumulative column leakage current in excess of the upper threshold value. For example, if each cell in a column of 512 cells leaks 0.2 microamps, the total column leakage current is 102.4 microamps, in excess of the reference current (nominally 100 microamps), thereby disabling the entire column. Milder cases may simply degrade the performance of the memory over time, greatly reducing the reliability and endurance of the device, i.e. the number of cycles the device can be successfully programmed and erased.
The problem of over-erasure is recognized. For example, the above noted U.S. Pat. No. 5,335,198, to Van Buskirk et al., discloses an over-erasure correction method, involving performing a program verification each time a cell is programmed. A cell is programmed by applying pulses of a predetermined relatively high voltage (e.g. 12 v) to the wordline (gate), with a predetermined mid level voltage (e.g. 5.5 v) applied to the bit line (drain); and the source grounded. The program verification entails, in essence, applying a predetermined number of pulses to the wordline, then reading the current from the selected bit line (monitoring the output of the comparator), and continuing to apply the pulses to the word line until the bit line current I.sub.BL drops below the reference level ((1/n)I.sub.REF). The programming pulses applied on the word line, in addition to programming (charging) the selected cell, also tend to cause the over-erased bits in the column (cells with drains connected to bit line) to be charged back toward a positive threshold voltage. Disadvantageously, charging the over-erased bits in an column of cells as part of the program verification can introduce considerable delay in the programming operation.
As miniaturization places even higher premiums on space, it becomes desirable to use less than a full column of cells to generate the reference current. Moreover, use of a full column of reference cells formed in conjunction with the core array (connected to the core array word-lines) is problematical when used in the context of single external voltage devices such as disclosed in U.S. Pat. No. 5,077,691 to Hadad, et al., issued Dec. 31, 1991, e.g., "5.0 Volt-only" memory devices. More particularly, in conventional devices, erasure is effected by applying a relatively high positive voltage to the common source of the cells, grounding the wordline (control gate) and letting the drain (bit line) float. Since the sources of the cells of reference array 114 are not connected to the common source (but are instead grounded), reference array 114 is not affected by the convention erasure process. However, in single external voltage devices, instead of providing a relatively high voltage to the source to effect discharge (erasure), a lower voltage, such as a typical power supply voltage (e.g., +5 volts), is applied to the source in conjunction with applying a relatively high magnitude negative voltage to the control gate (wordline) of the selected cells. Since little current flows through the control gate, the gate voltage can be generated using onboard charge pumps, thus eliminating the need for the second higher voltage power supply. However, since the control gates of the cells in reference array 114 are connected to the wordlines of the core array, the reference array is subjected to a negative potential applied between the control gate (e.g., at negative 10 volts) and source (e.g., at 0 volts), potentially altering the charge on the floating gates of the reference array cells. Thus, in single external power supply devices the reference array is typically located remotely from the core array and formed separately from the core array during the fabrication process.
However, it has been determined that since the reference cells are formed separately from the array cells, the variations in the reference cells from the cells in the array the reference current may not accurately reflect the current generated by an unprogrammed cell in array 104. Such deviation can erroneously cause over-erasure or under erasure. Accordingly, it is desirable to detect deviations in the reference cells from design values (e.g. the array cells) and either vary fabrication parameters to cure the deviation, or compensate for the deviations in operation. However, there has been no ready way to measure the actual threshold voltage of the reference cell and actual sense ratio.